This invention relates to digital information communication systems and, more particularly, to high throughput fault tolerant systems for communicating digital information. Specifically, the invention is directed to a method and apparatus for providing high throughput fault tolerant digital information communication in serial format rather than parallel format. More specifically, the invention is directed to a high throughput fault tolerant serial digital information communication method and apparatus preferably characterized by full duplex, bidirectional communication of digital information in the form of messages being communicated in serial format at a first rate and half duplex, unidirectional communication of digital information in the form of large blocks of data being communicated in serial format at a second higher rate.
Generally, the architectures of known information processing systems, such as general purpose programmable digital computer systems, can be classified as either tightly coupled or loosely coupled, the trend being toward the loosely coupled architecture. A centralized memory is shared in a tightly coupled information processing system, and a central communication controller handles communication among the individual information processing elements on a synchronous basis. The burden on the central communication controller can be significant, which can impair the throughput of the information processing system.
A loosely coupled information processing system is also referred to as a distributed information processing system. The centralized memory allocated to each of the information processing elements in the tightly coupled information processing system is replaced by a different architecture. In a loosely coupled information processing system, memory is distributed throughout the information processing elements. That is, each information processing element includes a stand-alone memory and a communication controller. The communication controllers handle communication among the information processing elements through a communication network.
The circuit implementation of the architecture in a loosely coupled information processing system can be less complicated than the circuit implementation of a tightly coupled information processing system due to a reduction in the complexity of the communication controller. Even more importantly, the proliferation of information processing elements, such as user terminals, add-on memory elements, and other input/output devices having stand-alone memory, which has occurred for extending the capabilities of the central information processing system, renders the information processing system conducive to a loosely coupled architecture.
Although the principles of the present invention are applicable to tightly coupled information processing systems, the high throughput fault tolerant serial digital communication method and apparatus in accordance with the invention are particularly advantageous in loosely coupled information processing systems. Therefore, the high throughput fault tolerant serial digital communication method and apparatus in accordance with the invention will be described by way of example in connection with loosely coupled information processing systems but should not be considered to be limited to use solely in a loosely coupled architecture.
One known technique for communicating digital information in a loosely coupled information processing system is single channel serial networking. Two common types of single channel serial communication network architectures have evolved. One architecture is known as Ethernet and is based on carrier sense multiple access with collision detection. The other architecture is based on token passing. Single channel serial network architectures are primarily intended for digital information communication among geographically diverse locations at one data rate and are characterized by a relatively low throughput and the lack of fault tolerance.
Another known technique for communicating digital information in a loosely coupled information processing system is parallel bus networking. A parallel bus network architecture is disclosed in Katzman et al., U.S. Pat. No. 4,228,496 and is incorporated into a computer system known as the Non-Stop (registered trademark) manufactured by Tandem Computers Incorporated of Cupertino, California. The parallel bus network architecture disclosed in Katzman et al., U.S. Pat. No. 4,228,496 enables digital information communication on each of two buses in parallel format, thereby increasing the throughput as compared to a single parallel bus network architecture. Furthermore, fault tolerance is provided based on the fact that if one bus is inoperative, for example, due to a short circuit or open circuit fault, the other parallel bus is used for all communication, notwithstanding the fact that the throughput capability decreases. Generally, the parallel bus network architectures have supplanted single channel serial network architectures for localized information processing systems, such as a computer system located within a single frame.
Unfortunately, the parallel bus network architecture, such as disclosed in Katzman et al., U.S. Pat. No. 4,228,496 has several disadvantages. The circuit implementation of a parallel bus network architecture is required to operate at high speeds and is complex. Furthermore, proliferation of parallel buses compounds the complexity of the circuit implementation and generally entails the festooning of significant amounts of additional ribbon cable, which complicates installation. The complexity of the circuit implementation of a parallel bus network architecture and the number of parallel buses renders the parallel bus network architecture very expensive. Although the throughput is relatively high compared with the single channel serial network architecture, the overall data rate is restricted by the fact that there is no capability for other than unidirectional communication of digital information on a bus. Furthermore, error checking is complex.
The method and apparatus for communicating digital information in accordance with the present invention obviate the problems heretofore experienced with both the single channel serial network architectures and the parallel bus network architecture. The method and apparatus in accordance with the invention for communicating digital information overcome the low data rate and lack of fault tolerance present in single channel serial network architectures by providing high throughput fault tolerant serial communication of digital information over communication circuits preferably characterized by messages being communicated at a first rate and substantial amounts of data being communicated at a second higher rate. The method and apparatus in accordance with the invention for serially communicating digital information also overcome the shortcomings of the parallel bus network architecture in several regards. The method and apparatus in accordance with the invention provide full duplex, bidirectional serial communication of digital information in the form of messages as compared to parallel unidirectional communication of all digital information in parallel bus network architectures, thereby increasing the throughput. Furthermore, the method and apparatus of the invention for serially communicating digital information facilitate error checking, thereby overcoming the difficulty of error checking in parallel bus network architectures. The method and apparatus in accordance with the invention for serially communicating digital information also reduce the complexity of the circuit implementation characteristic of parallel bus network architectures and the amount of ribbon cable needed, thereby reducing the cost of a high throughput fault tolerant digital information communication network for a loosely coupled information processing system.